TSMC N7, N7P and Intel 7 don't use EUV. It's all quad patterned DUV. DUV lithography has been in use since the 1990s going from 800nm to N7P.
Every single node after TSMC's so called 16nm has been all marketing. It would've more accurate to call TSMC 16FF as 20nm FinFET. This is why Intel brands what they themselves called 10nm as Intel 7 to bring their marketing more in line with TSMC's.
SMIC N+1 has a density of 89 million of transistors per mm² while TSMC N7 has 91.2. TSMC 10FF and Samsung 10LPP only offer slightly more than half that density.
That's based on TSMC's own test chip not an actual customer's. 17.92 mm² is incredibly tiny when SoCs, CPUs and GPUs range in size from 100 to 600 mm² increasing the proportion of chips with defects as the number of chips on the wafer drops.
From that very article
As TSMC themselves designed the chip, they definitely followed all their design rules for that process to maximize yield. No customer would do that.
Anand explains this in one of his articles.